At present, the superscalar architecture dominates over the advanced microprocessor field. The superscalar microprocessor architecture can send out and execute more than one instruction within one cycle to improve its performance. The key technique, however, is how to develop the parallelization of the instruction level.
The prior approach is to find the instructions capable of being executed in parallel within each basic block. The term of "basic block" is defined as the instruction region from one branch instruction to the next branch instruction. However, such an approach is limited by some problems such as the dependency of data, the conflict between resources, and the control branch problem, and thus cannot obtain a large parallel gain.
The statistical average number of the instructions in one basic block is only 12-16 or so. Therefore, the superscalar microprocessor cannot generally exhibit its full potential performance if it only utilizes the parallelization in individual basic block.
In order to enhance the performance, a speculative execution method is proposed. In this method, some instructions which are assumed to be determined later whether to be executed or not to be executed by the results of their related control branch instructions are speculatively executed before the results of the branch instructions come out. Since the speculative execution technique can eliminate the dependency resulted from the branch instruction, the superscalar microprocessor can simultaneously execute the instructions which come from different basic blocks to significantly enhance the available parallelization in a program.
Further, the Stanford University has proposed an instruction boosting concept which utilizes the shadow register file to allow the instruction boost between adjacent basic blocks, so that the parallelization among the instructions is enhanced, Referring to FIGS. 1, 2a and 2b, FIG. 1 shows the contents of three basic blocks 10, 12, and 14 before boosted, and FIG. 2a shows that an instruction "r4:=r3+r6" in the basic block 12' (LAB1) is boosted into the upper-level basic block 10'. In this situation, the output destination register must be changed into r4.S which is the shadow register of r4, as shown in FIG. 2b. After the branch instruction "beq.t r1, LAB 1" in the basic block 10' is executed, r4.S will be duplicated into the r4 position of the sequential register file 16 or alternatively be discarded, depending upon the result of the branch instruction. This technique, however, needs one shadow register file to support one-level boosting, and thus the hardware complexity is very high. Referring to FIGS. 3a and 3b, there is shown that two shadow register files are needed to support two-level instruction boosting (shown by two dotted arrows in FIG. 3a). The register r4 utilizes the shadow register file (r4.S1) to support one level boosting, and the register r6 utilizes the shadow register file (r6.S2) to support another level boosting, and the register r6 utilized the shadow register file (r6.S2) to support another level boosting. In this instruction boosting method, most of the registers are seldom in use, and the complexity of the duplicating circuits will severely affect the circuit design of the sequential register file. Therefore, its entire performance/cost are not as desired.